A hand-crafted layout design of a logic LSI can yield a high degree of circuit integration but the integration comes at the expense of time and a high cost. Therefore, the layout design by a hand-craft has become a non-realistic technique except for the design of those parts of general-purpose LSIs which are to be mass-produced. An automatic layout design is more practical. In this automatic layout design, placement of elements and wiring are carried out automatically using standard cells which are designed with their operations verified beforehand. It is usually described as "a standard cell system" or "a gate array system".
However, in this automatic design technique, it is quite difficult for a placement wiring program to attain the high density wiring that can be done by a layout designer. Conventionally in the automatic layout design a double layer wiring system is used whereby a vertical and a horizontal wiring are provided from different wiring layers respectively. Furthermore, in automatic layout designs of silicon gate MOS devices which have high integration and low power consumption, two kinds of wiring systems are used.
The first kind of wiring system is that which uses a double-layer wiring structure which consists of a gate metal layer composed of polysilicon (polycrystalline silicon) or the like constituting the gates of MOS transistors as a first (for example, vertical) wiring layer, and a low-resistance metal wiring layer composed of aluminum or the like for connection to the sources or drains of MOS transistors as a second (for example, horizontal) wiring layer.
In FIG. 1 shows this first kind of wiring structure. The numeral 1 indicates a cell bench where standard cells which will be described later are placed. The numeral 2 indicates a wiring region designated as the horizontal wiring channel. The numeral 3 indicates a standard cell which is obtained by implementing a logic gate, for example, an inverter, a 2-input NOR gate, or 3-input NAND gate, in a cell according to a layout design. The numeral 4 indicates a vertical wiring composed of a gate metal layer. The numeral 5 indicates a horizontal wiring composed of an aluminum wiring layer. The numeral 6 and 7 indicate a power supply wiring and a ground wiring respectively. The numeral 8 indicates an aluminum wiring used as a lead for a drain electrode. The numeral 9 indicates a contact for connecting between the diffused region and the aluminum wiring layer or between the gate metal layer and the aluminum wiring layer. The numeral 10 and 11 indicate a P-type impurity region and an N-type impurity region respectively. The numeral 40 indicates a P-well region.
In this type of wiring structure, wirings for input/output terminals of cells are wired by using vertical wirings 4 and horizontal wirings 5 in accordance with information for connections between the cells. The power supply wiring 6 and ground wiring 7 in the standard cell run in the horizontal direction, being composed of an aluminum wiring respectively. An output terminal of a logic gate is let out by a vertical wiring 4 of a gate metal layer through an aluminum wiring 8 which connects the drains of a P-channel transistor and a N-channel transistor. The drain of the P-channel transistor consists of the region 10 which is constructed by diffusing P-type impurities into the N-type semiconductor substrate. The drain of N-channel transistor consists of the N-type impurity region 11 which is produced by diffusing N-type impurities into the P-well region 40 which is produced by diffusing P-type impurities into the semiconductor substrate. A logic LSI is layed out by using standard cells and wiring regions of such structure. This conventional structure has as its feature the capability of realizing the LSI by the conventional wiring process of a polysilicon gate and single-layer aluminum.
The second kind of wiring system is that which uses a double layer aluminum wiring structure, mainly aiming to improve the operation speed of the first kind of wiring system. The structure is shown in FIG. 2.
In FIG. 2, it is a fundamental arrangement that horizontal wirings are constructed of a first low-resistance metal wiring layer 5 (a first aluminum wiring layer) and that vertical wirings are constructed of a second low-resistance metal wiring layer 13 (a second aluminum wiring layer), whereby wiring is carried out between the standard cells. In addition, a gate metal wiring layer 4 which has high-resistance relative to the first and second low-resistance wiring layer 5, 13 is used only for wiring in the standard cell, not being used in the wirings region between the cells. The numeral 12 indicates a through hole for connecting between the first and the second aluminum wiring.
One advantage of this system resides in that wiring is carried out by using low-resistance wiring layers, which results in only a small resistance due to the wirings, which allows the device to obtain a higher gate operation speed. Another advantage of this system is the ability to easily calculate the delay time of the gate which should be used in logical verifications and timing verifications of LSIs from only capacities, for example, capacitances of the wirings input capacitances of the logic gate which is to be driven, and so on.
However, it is non-advantageous to use a gate metal layer which has generally a high-resistance per unit length as a vertical wiring layer in view of operation speed of a logic LSI in the conventional semiconductor device, especially in the double-layer wiring structure described above as a first kind of wiring system. That is, in this double-layer wiring structure, it is fundamentally necessary to construct feed through wirings (not shown in FIG. 1) which are vertical wirings provided between the cells by gate metal wiring layers resulting in the increased length of the gate metal wiring and hence an increase in wiring resistance. The length of the gate metal wiring becomes also considerably lengthy when there is provided a vertical wiring region in order to increase the wiring density. In this case, a large resistance arises in the wiring, and the operation speed of the logic gate decreases significantly. Accordingly, it is necessary to add an element in the placement/wiring program that replace the gate metal wiring by an aluminum wiring in those regions where a long gate metal wiring does not cross with an aluminum wiring in order to avoid a slow down of the operation speed. Without this element it is unable to use the program in a design of a high speed LSI. Furthermore, it becomes difficult to predict or calculate the delay time of a logic gate before the production thereof because of its resistance.
Additionally, in the double-layer wiring structure which is described above as a second kind of wiring system, there is a disadvantage in that the gate metal wiring is only used for providing gate electrodes and not used for providing wirings. Furthermore, it is necessary to provide excess regions composed of the first metal (horizontal) wiring layer in order to connect the gate metal with the second metal (vertical) wiring layer, resulting in less than optional operation speed and a lower degree of integration of LSIs. This is because it is impossible to make the second metal wiring layer in contact with the gate metal directly because of the thickness of the insulating layer that is inserted between the layers in the manufacturing process for MOS devices or the like. Providing excess regions composed of the first metal wiring layer also prevents providing a feed through above the excess regions using the second metal wiring layer.